Alif Semiconductor /AE512F80F5582AS_CM55_HE_View /USB /DSTS

Connected Speed. Indicates the speed at which the USB controller has come up after speed detection through a chirp sequence.

0 (Val_0x0): High-speed (PHY clock is running at 30 or 60 MHz)

1 (Val_0x1): Full-speed (PHY clock is running at 30 or 60 MHz)

4 (Val_0x4): SuperSpeed (PHY clock is running at 125 or 250 MHz)

Frame/Microframe Number of the Received SOF. Bits 16-14 are not used. Software can ignore these 3 bits. Bits 13-3 indicate the frame number. Note: After power-on reset, the controller generates the microframe number internally for every 125 us if the USB host has not issued SOF/ITP yet. During P3 state, the duration of SOFFN is based on the SUSPEND_CLK frequency.

RxFIFO Empty.

USB/Link State. When Hibernation is enabled, the GCTL[GBLHIBERNATIONEN] = 0x1, the USBLNKST bit field is valid only when the DCTL[RUN_STOP] bit is set to 0x1 and the DCNRD = 0x0. The Early Suspend link state is an early indication of device suspend in HS/FS. The link state changes to Early Suspend after detecting bus idle for 3 ms. In HS operation, this is an indication that the USB bus (that is, LineState) has been in idle (SE0) for 3 ms. However, it does not confirm whether the next process is Suspend or Reset. The device checks the bus again after pull up enable delay and if the line state indicates Suspend (full speed J), then the device waits for an additional time (~3 ms) to indicate the actual Suspend state. In FS operation, this is an indication that the USB bus (that is, LineState) has been in idle (J) for 3 ms. The device waits for an additional time (~3 ms of Idle) to indicate the actual Suspend state.

0 (Val_0x0): On state

2 (Val_0x2): Sleep (L1) state

3 (Val_0x3): Suspend (L2) state

4 (Val_0x4): Disconnected state (Default state)

5 (Val_0x5): Early Suspend state (valid only when Hibernation is disabled, the GCTL[GBLHIBERNATIONEN] = 0x0)

14 (Val_0xE): Reset (valid only when Hibernation is enabled, the GCTL[GBLHIBERNATIONEN] = 0x1)

15 (Val_0xF): Resume (valid only when Hibernation is enabled, the GCTL[GBLHIBERNATIONEN] = 0x1)

Device Controller Halted. This bit is set to 0x0 when the DCTL[RUN_STOP] bit is set to 0x1. The controller sets this bit to 0x1 when, after software sets the DCTL[RUN_STOP] bit to 0x0, the controller is idle and the lower layer finishes the disconnect process. When this bit is set to 0x1, the controller does not generate Device events. Note: The controller does not set this bit to 0x1 if the GEVNTCOUNT0 register has some valid value. Software needs to acknowledge the events that are generated (by writing to the GEVNTCOUNT0 register) while it is waiting for this bit to be set to 0x1. When Interrupt Moderation is enabled, there could be delay in raising the interrupt line when the event count is non-zero. Software should read the GEVNTCOUNT0 register directly and acknowledge them.

Core Idle. The bit indicates that the controller finished transferring all RxFIFO data to system memory, writing out all completed descriptors, and all Event Counts are zero. Note: While testing for Reset values, mask out the read value. This bit represents the changing state of the controller and does not hold a static value.

SSS Save State Status. This bit is similar to the USBSTS[SSS] in host mode. When the controller has finished the save process, it completes the command by setting the SSS bit to 0x0.

RSS Restore State Status. This bit is similar to the USBSTS[RSS] bit in Host mode. When the controller finishes the restore process, it completes the command by setting the RSS bit to 0x0.

Save Restore Error. Currently not supported.

Device Controller Not Ready (not used).